Lectures on Reliability and Yield

Lecture 1: Insight about Design for Reliability and Application to circuits

The talk will cover a basics of reliability of microelectronics followed by different wear-out mechanisms for active devices. Modeling framework for circuit simulation is introduced. The talk will end by presenting some illustrations of reliability analysis for digital and RF/mmW circuits. 

Speaker bio: Florian Cacho, Device to Product Reliability Manager, STMicroelectronics, Crolles

Florian Cacho is managing the Device to Product Reliability (D2PR) team in ST Microelectrics, Crolles/France. He completed his Ph.D. in 2005 and he recently defended at Grenoble Institute of Technology and Habilitation to Steer Research (HDR) entitled: “From wear-out mechanisms in microelectronics circuits to reliability aware design methodologies for guarantying robust and resilient products”. He is working in ST for past 15+ years in Technology R&D department.

Lecture 2: Design Analysis for Circuit Reliability & Silicon Assessment 

The talk will cover impact of MOS Reliability and analysis for VLSI designs. Basic overview will also be provided for silicon qualification assessment of SOC & IP Reliability.

Speaker bio: Anuj Gupta, Group Manager, STMicroelectronics, Greater Noida

Anuj Gupta is an experienced semiconductor leader with more than two decades of experience working in ST Microelectronics, India. Has strong technical background on different aspects – IP and library design, technology, EDA flows and silicon qualification in wide range of semiconductor technologies. Currently working as Group Manager in Technology R&D for development and qualification of Analog & IOs Design Platforms.

Link for registration:  https://events.teams.microsoft.com/event/72cd4f41-0495-4820-98b1-09b30bc5bd69@403ee5f4-55b3-45cd-8ae2-824be887a075