IEEE Lafayette Section Young Professionals Affinity Group – IEEE Day Tech Chat

In this talk, the speaker will first discuss how new mapping solutions, i.e., composing heterogeneous accelerators within a system-on-chip with both FPGAs and AI tensor cores, achieve orders of magnitude energy efficiency gains when compared to monolithic accelerator mapping designs for deep learning applications. Then, the speaker will apply such novel mapping solutions to show how design space explorations are performed to achieve low-latency AI inference. The speaker will further discuss how we applied these techniques to different application domains, including autonomous vehicles, additive manufacturing, etc.